As part of the intellectual property (IP) design process, the IP vendor and the foundry negotiate the “waiver” of certain design rule checking (DRC) errors for the process to which the rule deck is targeted. However, when the IP is integrated into a full-chip design, these errors reappear in the full chip DRC results. With no effective way to identify these errors, chip designers must waste time debugging waived and false errors, and repeating the waiver communication process with the foundry.This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results. This new method enables chip designers to eliminate debug time previously spent on these errors, as well as time spent renegotiating waivers with the foundry. Automated waiver management not only helps designers achieve accurate DRC results in a timely and efficient manner, but also reduces time to market by eliminating unnecessary cycles from the verification flow.
DatacenterDynamics is a brand of DCD Group, a global B2B media and publishing company that develops products to help senior professionals in the world's most ICT dependent organizations make risk-based infrastructure and capacity decisions.
Our portfolio of live events, online and print publishing, business intelligence and professional development brands are centred on the complexities of technology convergence. Operating in 42 different countries, we have developed a unique global knowledge and networking platform, which is trusted by over 30,000 ICT, engineering and technology professionals.
Data Centre Dynamics Ltd.
102-108 Clifton Street
London EC2A 4HW